58 lines
2.5 KiB
Coq
58 lines
2.5 KiB
Coq
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module DataMemory(
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input reset ,
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input clk ,
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input MemRead ,
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input MemWrite ,
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input [32 -1:0] Address ,
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input [32 -1:0] Write_data ,
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output [32 -1:0] Read_data
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);
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// RAM size is 256 words, each word is 32 bits, valid address is 8 bits
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parameter RAM_SIZE = 256;
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parameter RAM_SIZE_BIT = 8;
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// RAM_data is an array of 256 32-bit registers
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reg [31:0] RAM_data [RAM_SIZE - 1: 0];
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// read data from RAM_data as Read_data
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assign Read_data = MemRead? RAM_data[Address[RAM_SIZE_BIT + 1:2]]: 32'h00000000;
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// write Write_data to RAM_data at clock posedge
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integer i;
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always @(posedge reset or posedge clk)begin
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if (reset) begin
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// -------- Paste Data Memory Configuration Below (Data-q1.txt)
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// Data Input: X = [[X11, X12, X13, X14, X15, X16, X17, X18], [X21, X22, X23, X24, X25, X26, X27, X28]]
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// Data Input: Y = [[Y11, Y12], [Y21, Y22], [Y31, Y32], [Y41, Y42], [Y51, Y52], [Y61, Y62], [Y71, Y72], [Y81, Y82]]
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// Data Output: Z = matmul(X,Y) = [[Z11, Z12], [Z21, Z22]]
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// Calculation in cpu: Z11 = X11*Y11 + X12*Y21 + X13*Y31 + X14*Y41 + X15*Y51 + X16*Y61 + X17*Y71 + X18*Y81
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// Calculation in cpu: Z12 = X11*Y12 + X12*Y22 + X13*Y32 + X14*Y42 + X15*Y52 + X16*Y62 + X17*Y72 + X18*Y82
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// Calculation in cpu: Z21 = X21*Y11 + X22*Y21 + X23*Y31 + X24*Y41 + X25*Y51 + X26*Y61 + X27*Y71 + X28*Y81
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// Calculation in cpu: Z22 = X21*Y12 + X22*Y22 + X23*Y32 + X24*Y42 + X25*Y52 + X26*Y62 + X27*Y72 + X28*Y82
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// paste in DataMemory.v
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RAM_data[0] <= 32'hd328fef9; // X11, X12, X13, X14, to be stored in $t0
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RAM_data[1] <= 32'h0324063a; // X15, X16, X17, X18, to be stored in $t1
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RAM_data[2] <= 32'h12da0c13; // X21, X22, X23, X24, to be stored in $t2
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RAM_data[3] <= 32'hde1015d6; // X25, X26, X27, X28, to be stored in $t3
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RAM_data[4] <= 32'hdaf20624; // Y11, Y21, Y31, Y41, to be stored in $t4
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RAM_data[5] <= 32'hc31f27c9; // Y51, Y61, Y71, Y81, to be stored in $t5
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RAM_data[6] <= 32'h3ce4c0c6; // Y12, Y22, Y32, Y42, to be stored in $t6
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RAM_data[7] <= 32'h12ea09c2; // Y52, Y62, Y72, Y82, to be stored in $t7
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for (i = 8; i < RAM_SIZE; i = i + 1)
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RAM_data[i] <= 32'h00000000;
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// -------- Paste Data Memory Configuration Above
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end
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else if (MemWrite) begin
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RAM_data[Address[RAM_SIZE_BIT + 1:2]] <= Write_data;
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end
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end
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endmodule
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