2024-06-29 06:20:54 +00:00
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module InstructionMemory(
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input [32 -1:0] Address,
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output reg [32 -1:0] Instruction
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);
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always @(*)
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case (Address[9:2])
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// -------- Paste Binary Instruction Below (Inst-q1-1/Inst-q1-2.txt)
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2024-06-30 16:24:09 +00:00
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8'd0: Instruction <= 32'h8c080000;
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8'd1: Instruction <= 32'h8c090004;
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8'd2: Instruction <= 32'h8c0a0008;
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8'd3: Instruction <= 32'h8c0b000c;
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8'd4: Instruction <= 32'h8c0c0010;
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8'd5: Instruction <= 32'h8c0d0014;
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8'd6: Instruction <= 32'h8c0e0018;
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8'd7: Instruction <= 32'h8c0f001c;
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8'd8: Instruction <= 32'h010c802d;
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8'd9: Instruction <= 32'h012d202d;
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8'd10: Instruction <= 32'h02048020;
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8'd11: Instruction <= 32'h010e882d;
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8'd12: Instruction <= 32'h012f202d;
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8'd13: Instruction <= 32'h02248820;
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8'd14: Instruction <= 32'h0200882e;
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8'd15: Instruction <= 32'h014c902d;
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8'd16: Instruction <= 32'h016d202d;
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8'd17: Instruction <= 32'h02449020;
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8'd18: Instruction <= 32'h014e982d;
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8'd19: Instruction <= 32'h016f202d;
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8'd20: Instruction <= 32'h02649820;
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8'd21: Instruction <= 32'h0240982e;
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8'd22: Instruction <= 32'hac100020;
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8'd23: Instruction <= 32'hac110024;
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8'd24: Instruction <= 32'hac120028;
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8'd25: Instruction <= 32'hac13002c;
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8'd26: Instruction <= 32'h0810001a;
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2024-06-30 15:01:11 +00:00
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2024-06-29 06:20:54 +00:00
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// -------- Paste Binary Instruction Above
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default: Instruction <= 32'h00000000;
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endcase
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endmodule
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