diff --git a/sources_1/imports/single-cycle/ALU.v b/sources_1/imports/single-cycle/ALU.v index fddecbd..7354d2a 100644 --- a/sources_1/imports/single-cycle/ALU.v +++ b/sources_1/imports/single-cycle/ALU.v @@ -7,8 +7,6 @@ module ALU( output reg [32 -1:0] out , output zero ); - reg signed [7:0] in11,in12,in13,in14,in21,in22,in23,in24; - reg [31:0] MACout; // zero means whether the output is zero or not assign zero = (out == 0); @@ -23,18 +21,7 @@ module ALU( assign lt_signed = (in1[31] ^ in2[31])? ((ss == 2'b01)? 0: 1): lt_31; - always @(*) - begin - in11=in1[31:24]; - in12=in1[23:16]; - in13=in1[15:8]; - in14=in1[7:0]; - in21=in2[31:24]; - in22=in2[23:16]; - in23=in2[15:8]; - in24=in2[7:0]; - MACout=in11*in21+in12*in22+in13*in23+in14*in24; - end + // different ALU operations always @(*) @@ -50,7 +37,6 @@ module ALU( 5'b11000: out <= (in2 >> in1[4:0]); 5'b11001: out <= ({{32{in2[31]}}, in2} >> in1[4:0]); 5'b11010: out <= in1 * in2; // mul - 5'b11011: out <= MACout; default: out <= 32'h00000000; endcase diff --git a/sources_1/imports/single-cycle/ALUControl.v b/sources_1/imports/single-cycle/ALUControl.v index 01e8bb2..336e26d 100644 --- a/sources_1/imports/single-cycle/ALUControl.v +++ b/sources_1/imports/single-cycle/ALUControl.v @@ -19,7 +19,6 @@ module ALUControl( parameter aluSRL = 5'b11000; parameter aluSRA = 5'b11001; parameter aluMUL = 5'b11010; //mul - parameter aluMAC = 5'b11011; // Sign means whether the ALU treats the input as a signed number or an unsigned number assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3]; @@ -41,7 +40,6 @@ module ALUControl( 6'b10_0111: aluFunct <= aluNOR; 6'b10_1010: aluFunct <= aluSLT; 6'b10_1011: aluFunct <= aluSLT; - 6'b10_1101: aluFunct <= aluMAC; default: aluFunct <= aluADD; endcase diff --git a/sources_1/imports/single-cycle/Control.v b/sources_1/imports/single-cycle/Control.v index b439f8d..1f27043 100644 --- a/sources_1/imports/single-cycle/Control.v +++ b/sources_1/imports/single-cycle/Control.v @@ -48,7 +48,7 @@ module Control( 1'b1; assign LuOp = (OpCode == 6'h0f)? 1'b1: - 1'b0; + 1'b0; // Your code above (for question 1) // set ALUOp diff --git a/sources_1/imports/single-cycle/DataMemory.v b/sources_1/imports/single-cycle/DataMemory.v index f8e28e1..5a48f5c 100644 --- a/sources_1/imports/single-cycle/DataMemory.v +++ b/sources_1/imports/single-cycle/DataMemory.v @@ -23,30 +23,28 @@ module DataMemory( always @(posedge reset or posedge clk)begin if (reset) begin // -------- Paste Data Memory Configuration Below (Data-q1.txt) - // Data Input: X = [[X11, X12, X13, X14, X15, X16, X17, X18], [X21, X22, X23, X24, X25, X26, X27, X28]] - // Data Input: Y = [[Y11, Y12], [Y21, Y22], [Y31, Y32], [Y41, Y42], [Y51, Y52], [Y61, Y62], [Y71, Y72], [Y81, Y82]] - - // Data Output: Z = matmul(X,Y) = [[Z11, Z12], [Z21, Z22]] - - // Calculation in cpu: Z11 = X11*Y11 + X12*Y21 + X13*Y31 + X14*Y41 + X15*Y51 + X16*Y61 + X17*Y71 + X18*Y81 - // Calculation in cpu: Z12 = X11*Y12 + X12*Y22 + X13*Y32 + X14*Y42 + X15*Y52 + X16*Y62 + X17*Y72 + X18*Y82 - // Calculation in cpu: Z21 = X21*Y11 + X22*Y21 + X23*Y31 + X24*Y41 + X25*Y51 + X26*Y61 + X27*Y71 + X28*Y81 - // Calculation in cpu: Z22 = X21*Y12 + X22*Y22 + X23*Y32 + X24*Y42 + X25*Y52 + X26*Y62 + X27*Y72 + X28*Y82 - - // paste in DataMemory.v - - RAM_data[0] <= 32'hd328fef9; // X11, X12, X13, X14, to be stored in $t0 - RAM_data[1] <= 32'h0324063a; // X15, X16, X17, X18, to be stored in $t1 - RAM_data[2] <= 32'h12da0c13; // X21, X22, X23, X24, to be stored in $t2 - RAM_data[3] <= 32'hde1015d6; // X25, X26, X27, X28, to be stored in $t3 - - RAM_data[4] <= 32'hdaf20624; // Y11, Y21, Y31, Y41, to be stored in $t4 - RAM_data[5] <= 32'hc31f27c9; // Y51, Y61, Y71, Y81, to be stored in $t5 - RAM_data[6] <= 32'h3ce4c0c6; // Y12, Y22, Y32, Y42, to be stored in $t6 - RAM_data[7] <= 32'h12ea09c2; // Y52, Y62, Y72, Y82, to be stored in $t7 - - for (i = 8; i < RAM_SIZE; i = i + 1) - RAM_data[i] <= 32'h00000000; + // Data Input: X = [X0, X1, X2, X3] + // Data Input: Y = [Y0, Y1, Y2, Y3] + + // Data Output: Z = mac(X, Y) = X0*Y0 + X1*Y1 + X2*Y2 + X3*Y3 + + // paste in DataMemory.v + + RAM_data[0] <= 32'hffffffd3; // X0 = -45 + RAM_data[1] <= 32'h00000003; // Y0 = 3 + + RAM_data[2] <= 32'h00000028; // X1 = 40 + RAM_data[3] <= 32'h00000024; // Y1 = 36 + + + RAM_data[4] <= 32'hfffffffe; // X2 = -2 + RAM_data[5] <= 32'h00000006; // Y2 = 6 + + RAM_data[6] <= 32'hfffffff9; // X3 = -7 + RAM_data[7] <= 32'h0000003a; // Y3 = 58 + + for (i = 8; i < RAM_SIZE; i = i + 1) + RAM_data[i] <= 32'h00000000; // -------- Paste Data Memory Configuration Above end else if (MemWrite) begin diff --git a/sources_1/imports/single-cycle/InstructionMemory.v b/sources_1/imports/single-cycle/InstructionMemory.v index 5ab3594..4228a83 100644 --- a/sources_1/imports/single-cycle/InstructionMemory.v +++ b/sources_1/imports/single-cycle/InstructionMemory.v @@ -7,31 +7,18 @@ module InstructionMemory( case (Address[9:2]) // -------- Paste Binary Instruction Below (Inst-q1-1/Inst-q1-2.txt) - 8'd0: Instruction <= 32'h8c080000; - 8'd1: Instruction <= 32'h8c090004; - 8'd2: Instruction <= 32'h8c0a0008; - 8'd3: Instruction <= 32'h8c0b000c; - 8'd4: Instruction <= 32'h8c0c0010; - 8'd5: Instruction <= 32'h8c0d0014; - 8'd6: Instruction <= 32'h8c0e0018; - 8'd7: Instruction <= 32'h8c0f001c; - 8'd8: Instruction <= 32'h010c802d; - 8'd9: Instruction <= 32'h012d202d; - 8'd10: Instruction <= 32'h02048020; - 8'd11: Instruction <= 32'h010e882d; - 8'd12: Instruction <= 32'h012f202d; - 8'd13: Instruction <= 32'h02248820; - 8'd14: Instruction <= 32'h014c902d; - 8'd15: Instruction <= 32'h016d202d; - 8'd16: Instruction <= 32'h02449020; - 8'd17: Instruction <= 32'h014e982d; - 8'd18: Instruction <= 32'h016f202d; - 8'd19: Instruction <= 32'h02649820; - 8'd20: Instruction <= 32'hac100020; - 8'd21: Instruction <= 32'hac110024; - 8'd22: Instruction <= 32'hac120028; - 8'd23: Instruction <= 32'hac13002c; - 8'd24: Instruction <= 32'h08100018; + 8'd0: Instruction <= 32'h20040000; + 8'd1: Instruction <= 32'h20050020; + 8'd2: Instruction <= 32'h20100000; + 8'd3: Instruction <= 32'h8c880000; + 8'd4: Instruction <= 32'h8c890004; + 8'd5: Instruction <= 32'h71095002; + 8'd6: Instruction <= 32'h020a8020; + 8'd7: Instruction <= 32'h20840008; + 8'd8: Instruction <= 32'h10850001; + 8'd9: Instruction <= 32'h08100003; + 8'd10: Instruction <= 32'hacb00000; + 8'd11: Instruction <= 32'h0810000b; // -------- Paste Binary Instruction Above default: Instruction <= 32'h00000000; endcase