From a58a38c291f89d20dd226e33cf502e04c36b474b Mon Sep 17 00:00:00 2001 From: ClF3 Date: Mon, 1 Jul 2024 00:24:09 +0800 Subject: [PATCH] bug fixed --- sources_1/imports/single-cycle/CPU.v | 15 +++-- sources_1/imports/single-cycle/Control.v | 4 +- .../imports/single-cycle/InstructionMemory.v | 55 ++++++++++--------- sources_1/imports/single-cycle/RegisterFile.v | 8 ++- 4 files changed, 46 insertions(+), 36 deletions(-) diff --git a/sources_1/imports/single-cycle/CPU.v b/sources_1/imports/single-cycle/CPU.v index 255ea4d..2c96b41 100644 --- a/sources_1/imports/single-cycle/CPU.v +++ b/sources_1/imports/single-cycle/CPU.v @@ -69,20 +69,27 @@ module CPU( wire [32 -1:0] Databus3; wire [32 -1:0] Databus4; wire [5 -1:0] Write_register; + wire [5 -1:0] Write_register2; + wire [5 -1:0] Read_register1; wire [5 -1:0] Read_register2; - assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: (RegDst == 2'b01)? Instruction[15:11]:(RegDst == 2'b11)?Instruction[25:21]:5'b11111; - assign Read_register2 = (ReadFrom == 1'b1)? Instruction[15:11]: Instruction[20:16]; + assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: + (RegDst == 2'b01)? Instruction[15:11]: + (RegDst == 2'b11)? Instruction[25:21]: + 5'b11111; + assign Write_register2 = Instruction[15:11]; + assign Read_register1 = Instruction[25:21]; + assign Read_register2 = (ReadFrom == 1'b1)? Instruction[15:11]: Instruction[20:16]; RegisterFile register_file1( .reset (reset ), .clk (clk ), .RegWrite (RegWrite ), .Regwrite2 (RegWrite2 ), - .Read_register1 (Instruction[25:21] ), + .Read_register1 (Read_register1 ), .Read_register2 (Read_register2 ), .Write_register (Write_register ), - .Write_register2(Instruction[15:11] ), + .Write_register2(Write_register2 ), .Write_data (Databus3 ), .Write_data2 (Databus4 ), .Read_data1 (Databus1 ), diff --git a/sources_1/imports/single-cycle/Control.v b/sources_1/imports/single-cycle/Control.v index d05b762..c6f2e83 100644 --- a/sources_1/imports/single-cycle/Control.v +++ b/sources_1/imports/single-cycle/Control.v @@ -33,13 +33,13 @@ module Control( (OpCode == 6'h00 && Funct == 6'h2e)? 1'b1: 1'b0; assign ReadFrom = - (OpCode == 6'h00 || OpCode == 6'h2e)? 1'b1: + (OpCode == 6'h00 && Funct == 6'h2e)? 1'b1: 1'b0; assign RegDst = (OpCode[5:3] == 3'b001)? 2'b00: (OpCode == 6'h23)? 2'b00: (OpCode == 6'h03)? 2'b10: - (OpCode == 6'h2e)? 2'b11: + (OpCode == 6'h00 && Funct == 6'h2e)? 2'b11: 2'b01; assign MemRead = (OpCode == 6'h23)? 1'b1: 1'b0; assign MemWrite = (OpCode == 6'h2b)? 1'b1: 1'b0; diff --git a/sources_1/imports/single-cycle/InstructionMemory.v b/sources_1/imports/single-cycle/InstructionMemory.v index fffd32b..5b74a29 100644 --- a/sources_1/imports/single-cycle/InstructionMemory.v +++ b/sources_1/imports/single-cycle/InstructionMemory.v @@ -7,33 +7,34 @@ module InstructionMemory( case (Address[9:2]) // -------- Paste Binary Instruction Below (Inst-q1-1/Inst-q1-2.txt) - 8'd0: Instruction <= 32'h8c080000; - 8'd1: Instruction <= 32'h8c090004; - 8'd2: Instruction <= 32'h8c0a0008; - 8'd3: Instruction <= 32'h8c0b000c; - 8'd4: Instruction <= 32'h8c0c0010; - 8'd5: Instruction <= 32'h8c0d0014; - 8'd6: Instruction <= 32'h8c0e0018; - 8'd7: Instruction <= 32'h8c0f001c; - 8'd8: Instruction <= 32'h010c802d; - 8'd9: Instruction <= 32'h012d202d; - 8'd10: Instruction <= 32'h02048020; - 8'd11: Instruction <= 32'h010e882d; - 8'd12: Instruction <= 32'h012f202d; - 8'd13: Instruction <= 32'h02248820; - 8'd14: Instruction <= 32'h0200882e; - 8'd15: Instruction <= 32'h014c902d; - 8'd16: Instruction <= 32'h016d202d; - 8'd17: Instruction <= 32'h02449020; - 8'd18: Instruction <= 32'h014e982d; - 8'd19: Instruction <= 32'h016f202d; - 8'd20: Instruction <= 32'h02649820; - 8'd21: Instruction <= 32'h0240982e; - 8'd22: Instruction <= 32'hac100020; - 8'd23: Instruction <= 32'hac110024; - 8'd24: Instruction <= 32'hac120028; - 8'd25: Instruction <= 32'hac13002c; - 8'd26: Instruction <= 32'h0810001a; +8'd0: Instruction <= 32'h8c080000; +8'd1: Instruction <= 32'h8c090004; +8'd2: Instruction <= 32'h8c0a0008; +8'd3: Instruction <= 32'h8c0b000c; +8'd4: Instruction <= 32'h8c0c0010; +8'd5: Instruction <= 32'h8c0d0014; +8'd6: Instruction <= 32'h8c0e0018; +8'd7: Instruction <= 32'h8c0f001c; +8'd8: Instruction <= 32'h010c802d; +8'd9: Instruction <= 32'h012d202d; +8'd10: Instruction <= 32'h02048020; +8'd11: Instruction <= 32'h010e882d; +8'd12: Instruction <= 32'h012f202d; +8'd13: Instruction <= 32'h02248820; +8'd14: Instruction <= 32'h0200882e; +8'd15: Instruction <= 32'h014c902d; +8'd16: Instruction <= 32'h016d202d; +8'd17: Instruction <= 32'h02449020; +8'd18: Instruction <= 32'h014e982d; +8'd19: Instruction <= 32'h016f202d; +8'd20: Instruction <= 32'h02649820; +8'd21: Instruction <= 32'h0240982e; +8'd22: Instruction <= 32'hac100020; +8'd23: Instruction <= 32'hac110024; +8'd24: Instruction <= 32'hac120028; +8'd25: Instruction <= 32'hac13002c; +8'd26: Instruction <= 32'h0810001a; + // -------- Paste Binary Instruction Above default: Instruction <= 32'h00000000; diff --git a/sources_1/imports/single-cycle/RegisterFile.v b/sources_1/imports/single-cycle/RegisterFile.v index ae6dd1f..ea92e58 100644 --- a/sources_1/imports/single-cycle/RegisterFile.v +++ b/sources_1/imports/single-cycle/RegisterFile.v @@ -28,10 +28,12 @@ module RegisterFile( if (reset) for (i = 1; i < 32; i = i + 1) RF_data[i] <= 32'h00000000; - else if (RegWrite && (Write_register != 5'b00000)) + else + begin + if (RegWrite && (Write_register != 5'b00000)) RF_data[Write_register] <= Write_data; - else if (Regwrite2 && (Write_register2 != 5'b00000)) + if (Regwrite2 && (Write_register2 != 5'b00000)) RF_data[Write_register2] <= Write_data2; - + end endmodule \ No newline at end of file