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MIPS_Processor
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compare: tianyi:a06e4e1d5600fa79329d0983fc019c7cb1c90ea1
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419a239a05 ... a06e4e1d56

Author SHA1 Message Date
ClF3 a06e4e1d56 ignored *.dcp 2024-07-01 17:21:22 +08:00
ClF3 27ff56bd0e updated .gitignore 2024-07-01 17:19:44 +08:00
3 changed files with 1 additions and 30 deletions
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.gitignore vendored Normal file
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*.dcp

30
sources_1/imports/single-cycle/test_cpu.v
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module test_cpu();
reg reset ;
reg clk ;
wire MemRead ;
wire MemWrite ;
wire [31:0] MemBus_Address ;
wire [31:0] MemBus_Write_Data ;
wire [31:0] Device_Read_Data ;
CPU cpu1(
.reset (reset ),
.clk (clk ),
.MemBus_Address (MemBus_Address ),
.Device_Read_Data (Device_Read_Data ),
.MemBus_Write_Data (MemBus_Write_Data ),
.MemRead (MemRead ),
.MemWrite (MemWrite )
);
initial begin
reset = 1;
clk = 1;
#100 reset = 0;
end
always #50 clk = ~clk;
endmodule

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utils_1/imports/synth_1/test_cpu.dcp
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