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ClF3 c4312e9350 updated .gitignore 2024-07-01 18:31:42 +08:00
3 changed files with 0 additions and 30 deletions

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module test_cpu();
reg reset ;
reg clk ;
wire MemRead ;
wire MemWrite ;
wire [31:0] MemBus_Address ;
wire [31:0] MemBus_Write_Data ;
wire [31:0] Device_Read_Data ;
CPU cpu1(
.reset (reset ),
.clk (clk ),
.MemBus_Address (MemBus_Address ),
.Device_Read_Data (Device_Read_Data ),
.MemBus_Write_Data (MemBus_Write_Data ),
.MemRead (MemRead ),
.MemWrite (MemWrite )
);
initial begin
reset = 1;
clk = 1;
#100 reset = 0;
end
always #50 clk = ~clk;
endmodule

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