tianyi
/
MIPS_Processor
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: tianyi:relu
Branches Tags
tianyi:relu
tianyi:mac
tianyi:basic
..
compare: tianyi:basic
Branches Tags
tianyi:mac
tianyi:relu
tianyi:basic

3 Commits
relu ... basic

Author SHA1 Message Date
ClF3 a06e4e1d56 ignored *.dcp 2024-07-01 17:21:22 +08:00
ClF3 27ff56bd0e updated .gitignore 2024-07-01 17:19:44 +08:00
ClF3 419a239a05 recover to q1 2024-07-01 01:16:30 +08:00
8 changed files with 46 additions and 128 deletions
Show Stats Expand all files Collapse all files

2
.gitignore vendored
View File

@ -1 +1 @@
*.dcp *.dcp

31
sources_1/imports/single-cycle/ALU.v
View File

@ -4,12 +4,9 @@ module ALU(
input [32 -1:0] in2 , input [32 -1:0] in2 ,
input [5 -1:0] ALUCtl , input [5 -1:0] ALUCtl ,
input Sign , input Sign ,
output reg [32 -1:0] out, out2, output reg [32 -1:0] out ,
output zero output zero
); );
reg signed [7:0] in11,in12,in13,in14,in21,in22,in23,in24;
reg [31:0] MACout;
reg signed [31:0] in1s, in2s;
// zero means whether the output is zero or not // zero means whether the output is zero or not
assign zero = (out == 0); assign zero = (out == 0);
@ -24,18 +21,7 @@ module ALU(
assign lt_signed = (in1[31] ^ in2[31])? assign lt_signed = (in1[31] ^ in2[31])?
((ss == 2'b01)? 0: 1): lt_31; ((ss == 2'b01)? 0: 1): lt_31;
always @(*)
begin
in11=in1[31:24];
in12=in1[23:16];
in13=in1[15:8];
in14=in1[7:0];
in21=in2[31:24];
in22=in2[23:16];
in23=in2[15:8];
in24=in2[7:0];
MACout=in11*in21+in12*in22+in13*in23+in14*in24;
end
// different ALU operations // different ALU operations
always @(*) always @(*)
@ -51,20 +37,9 @@ module ALU(
5'b11000: out <= (in2 >> in1[4:0]); 5'b11000: out <= (in2 >> in1[4:0]);
5'b11001: out <= ({{32{in2[31]}}, in2} >> in1[4:0]); 5'b11001: out <= ({{32{in2[31]}}, in2} >> in1[4:0]);
5'b11010: out <= in1 * in2; // mul 5'b11010: out <= in1 * in2; // mul
5'b11011: out <= MACout;
5'b11100: out <= in1s>0?in1s:0;
default: out <= 32'h00000000; default: out <= 32'h00000000;
endcase endcase
always @(*)
begin
in1s <= in1;
in2s <= in2;
end
always @(*)
case(ALUCtl)
5'b11100: out2 <= in2s>0?in2s:0;
default: out2 <= 32'h00000000;
endcase

4
sources_1/imports/single-cycle/ALUControl.v
View File

@ -19,8 +19,6 @@ module ALUControl(
parameter aluSRL = 5'b11000; parameter aluSRL = 5'b11000;
parameter aluSRA = 5'b11001; parameter aluSRA = 5'b11001;
parameter aluMUL = 5'b11010; //mul parameter aluMUL = 5'b11010; //mul
parameter aluMAC = 5'b11011;
parameter aluRELU= 5'b11100;
// Sign means whether the ALU treats the input as a signed number or an unsigned number // Sign means whether the ALU treats the input as a signed number or an unsigned number
assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3]; assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3];
@ -42,8 +40,6 @@ module ALUControl(
6'b10_0111: aluFunct <= aluNOR; 6'b10_0111: aluFunct <= aluNOR;
6'b10_1010: aluFunct <= aluSLT; 6'b10_1010: aluFunct <= aluSLT;
6'b10_1011: aluFunct <= aluSLT; 6'b10_1011: aluFunct <= aluSLT;
6'b10_1101: aluFunct <= aluMAC;
6'b10_1110: aluFunct <= aluRELU;
default: aluFunct <= aluADD; default: aluFunct <= aluADD;
endcase endcase

26
sources_1/imports/single-cycle/CPU.v
View File

@ -29,7 +29,6 @@ module CPU(
); );
// Control // Control
wire ReadFrom ;
wire [2 -1:0] RegDst ; wire [2 -1:0] RegDst ;
wire [2 -1:0] PCSrc ; wire [2 -1:0] PCSrc ;
wire Branch ; wire Branch ;
@ -42,7 +41,6 @@ module CPU(
wire ExtOp ; wire ExtOp ;
wire LuOp ; wire LuOp ;
wire RegWrite ; wire RegWrite ;
wire RegWrite2 ;
Control control1( Control control1(
.OpCode (Instruction[31:26] ), .OpCode (Instruction[31:26] ),
@ -50,8 +48,6 @@ module CPU(
.PCSrc (PCSrc ), .PCSrc (PCSrc ),
.Branch (Branch ), .Branch (Branch ),
.RegWrite (RegWrite ), .RegWrite (RegWrite ),
.RegWrite2 (RegWrite2 ),
.ReadFrom (ReadFrom ),
.RegDst (RegDst ), .RegDst (RegDst ),
.MemRead (MemRead ), .MemRead (MemRead ),
.MemWrite (MemWrite ), .MemWrite (MemWrite ),
@ -67,31 +63,18 @@ module CPU(
wire [32 -1:0] Databus1; wire [32 -1:0] Databus1;
wire [32 -1:0] Databus2; wire [32 -1:0] Databus2;
wire [32 -1:0] Databus3; wire [32 -1:0] Databus3;
wire [32 -1:0] Databus4;
wire [5 -1:0] Write_register; wire [5 -1:0] Write_register;
wire [5 -1:0] Write_register2;
wire [5 -1:0] Read_register1;
wire [5 -1:0] Read_register2;
assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: (RegDst == 2'b01)? Instruction[15:11]: 5'b11111;
(RegDst == 2'b01)? Instruction[15:11]:
(RegDst == 2'b11)? Instruction[25:21]:
5'b11111;
assign Write_register2 = Instruction[15:11];
assign Read_register1 = Instruction[25:21];
assign Read_register2 = (ReadFrom == 1'b1)? Instruction[15:11]: Instruction[20:16];
RegisterFile register_file1( RegisterFile register_file1(
.reset (reset ), .reset (reset ),
.clk (clk ), .clk (clk ),
.RegWrite (RegWrite ), .RegWrite (RegWrite ),
.Regwrite2 (RegWrite2 ), .Read_register1 (Instruction[25:21] ),
.Read_register1 (Read_register1 ), .Read_register2 (Instruction[20:16] ),
.Read_register2 (Read_register2 ),
.Write_register (Write_register ), .Write_register (Write_register ),
.Write_register2(Write_register2 ),
.Write_data (Databus3 ), .Write_data (Databus3 ),
.Write_data2 (Databus4 ),
.Read_data1 (Databus1 ), .Read_data1 (Databus1 ),
.Read_data2 (Databus2 ) .Read_data2 (Databus2 )
); );
@ -129,7 +112,6 @@ module CPU(
.ALUCtl (ALUCtl ), .ALUCtl (ALUCtl ),
.Sign (Sign ), .Sign (Sign ),
.out (ALU_out ), .out (ALU_out ),
.out2 (Databus4 ),
.zero (Zero ) .zero (Zero )
); );

13
sources_1/imports/single-cycle/Control.v
View File

@ -5,8 +5,6 @@ module Control(
output [2 -1:0] PCSrc , output [2 -1:0] PCSrc ,
output Branch , output Branch ,
output RegWrite , output RegWrite ,
output RegWrite2 ,
output ReadFrom ,
output [2 -1:0] RegDst , output [2 -1:0] RegDst ,
output MemRead , output MemRead ,
output MemWrite , output MemWrite ,
@ -29,17 +27,10 @@ module Control(
(OpCode == 6'h2b || OpCode == 6'h04 || OpCode == 6'h02)? 1'b0: (OpCode == 6'h2b || OpCode == 6'h04 || OpCode == 6'h02)? 1'b0:
(OpCode == 6'h00 && Funct == 6'h08)? 1'b0: (OpCode == 6'h00 && Funct == 6'h08)? 1'b0:
1'b1; 1'b1;
assign RegWrite2 =
(OpCode == 6'h00 && Funct == 6'h2e)? 1'b1:
1'b0;
assign ReadFrom =
(OpCode == 6'h00 && Funct == 6'h2e)? 1'b1:
1'b0;
assign RegDst = assign RegDst =
(OpCode[5:3] == 3'b001)? 2'b00: (OpCode[5:3] == 3'b001)? 2'b00:
(OpCode == 6'h23)? 2'b00: (OpCode == 6'h23)? 2'b00:
(OpCode == 6'h03)? 2'b10: (OpCode == 6'h03)? 2'b10:
(OpCode == 6'h00 && Funct == 6'h2e)? 2'b11:
2'b01; 2'b01;
assign MemRead = (OpCode == 6'h23)? 1'b1: 1'b0; assign MemRead = (OpCode == 6'h23)? 1'b1: 1'b0;
assign MemWrite = (OpCode == 6'h2b)? 1'b1: 1'b0; assign MemWrite = (OpCode == 6'h2b)? 1'b1: 1'b0;
@ -57,7 +48,7 @@ module Control(
1'b1; 1'b1;
assign LuOp = assign LuOp =
(OpCode == 6'h0f)? 1'b1: (OpCode == 6'h0f)? 1'b1:
1'b0; 1'b0;
// Your code above (for question 1) // Your code above (for question 1)
// set ALUOp // set ALUOp

46
sources_1/imports/single-cycle/DataMemory.v
View File

@ -23,30 +23,28 @@ module DataMemory(
always @(posedge reset or posedge clk)begin always @(posedge reset or posedge clk)begin
if (reset) begin if (reset) begin
// -------- Paste Data Memory Configuration Below (Data-q1.txt) // -------- Paste Data Memory Configuration Below (Data-q1.txt)
// Data Input: X = [[X11, X12, X13, X14, X15, X16, X17, X18], [X21, X22, X23, X24, X25, X26, X27, X28]] // Data Input: X = [X0, X1, X2, X3]
// Data Input: Y = [[Y11, Y12], [Y21, Y22], [Y31, Y32], [Y41, Y42], [Y51, Y52], [Y61, Y62], [Y71, Y72], [Y81, Y82]] // Data Input: Y = [Y0, Y1, Y2, Y3]
// Data Output: Z = matmul(X,Y) = [[Z11, Z12], [Z21, Z22]] // Data Output: Z = mac(X, Y) = X0*Y0 + X1*Y1 + X2*Y2 + X3*Y3
// Calculation in cpu: Z11 = X11*Y11 + X12*Y21 + X13*Y31 + X14*Y41 + X15*Y51 + X16*Y61 + X17*Y71 + X18*Y81 // paste in DataMemory.v
// Calculation in cpu: Z12 = X11*Y12 + X12*Y22 + X13*Y32 + X14*Y42 + X15*Y52 + X16*Y62 + X17*Y72 + X18*Y82
// Calculation in cpu: Z21 = X21*Y11 + X22*Y21 + X23*Y31 + X24*Y41 + X25*Y51 + X26*Y61 + X27*Y71 + X28*Y81 RAM_data[0] <= 32'hffffffd3; // X0 = -45
// Calculation in cpu: Z22 = X21*Y12 + X22*Y22 + X23*Y32 + X24*Y42 + X25*Y52 + X26*Y62 + X27*Y72 + X28*Y82 RAM_data[1] <= 32'h00000003; // Y0 = 3
// paste in DataMemory.v RAM_data[2] <= 32'h00000028; // X1 = 40
RAM_data[3] <= 32'h00000024; // Y1 = 36
RAM_data[0] <= 32'hd328fef9; // X11, X12, X13, X14, to be stored in $t0
RAM_data[1] <= 32'h0324063a; // X15, X16, X17, X18, to be stored in $t1
RAM_data[2] <= 32'h12da0c13; // X21, X22, X23, X24, to be stored in $t2 RAM_data[4] <= 32'hfffffffe; // X2 = -2
RAM_data[3] <= 32'hde1015d6; // X25, X26, X27, X28, to be stored in $t3 RAM_data[5] <= 32'h00000006; // Y2 = 6
RAM_data[4] <= 32'hdaf20624; // Y11, Y21, Y31, Y41, to be stored in $t4 RAM_data[6] <= 32'hfffffff9; // X3 = -7
RAM_data[5] <= 32'hc31f27c9; // Y51, Y61, Y71, Y81, to be stored in $t5 RAM_data[7] <= 32'h0000003a; // Y3 = 58
RAM_data[6] <= 32'h3ce4c0c6; // Y12, Y22, Y32, Y42, to be stored in $t6
RAM_data[7] <= 32'h12ea09c2; // Y52, Y62, Y72, Y82, to be stored in $t7 for (i = 8; i < RAM_SIZE; i = i + 1)
RAM_data[i] <= 32'h00000000;
for (i = 8; i < RAM_SIZE; i = i + 1)
RAM_data[i] <= 32'h00000000;
// -------- Paste Data Memory Configuration Above // -------- Paste Data Memory Configuration Above
end end
else if (MemWrite) begin else if (MemWrite) begin

41
sources_1/imports/single-cycle/InstructionMemory.v
View File

@ -7,35 +7,18 @@ module InstructionMemory(
case (Address[9:2]) case (Address[9:2])
// -------- Paste Binary Instruction Below (Inst-q1-1/Inst-q1-2.txt) // -------- Paste Binary Instruction Below (Inst-q1-1/Inst-q1-2.txt)
8'd0: Instruction <= 32'h8c080000; 8'd0: Instruction <= 32'h20040000;
8'd1: Instruction <= 32'h8c090004; 8'd1: Instruction <= 32'h20050020;
8'd2: Instruction <= 32'h8c0a0008; 8'd2: Instruction <= 32'h20100000;
8'd3: Instruction <= 32'h8c0b000c; 8'd3: Instruction <= 32'h8c880000;
8'd4: Instruction <= 32'h8c0c0010; 8'd4: Instruction <= 32'h8c890004;
8'd5: Instruction <= 32'h8c0d0014; 8'd5: Instruction <= 32'h71095002;
8'd6: Instruction <= 32'h8c0e0018; 8'd6: Instruction <= 32'h020a8020;
8'd7: Instruction <= 32'h8c0f001c; 8'd7: Instruction <= 32'h20840008;
8'd8: Instruction <= 32'h010c802d; 8'd8: Instruction <= 32'h10850001;
8'd9: Instruction <= 32'h012d202d; 8'd9: Instruction <= 32'h08100003;
8'd10: Instruction <= 32'h02048020; 8'd10: Instruction <= 32'hacb00000;
8'd11: Instruction <= 32'h010e882d; 8'd11: Instruction <= 32'h0810000b;
8'd12: Instruction <= 32'h012f202d;
8'd13: Instruction <= 32'h02248820;
8'd14: Instruction <= 32'h0200882e;
8'd15: Instruction <= 32'h014c902d;
8'd16: Instruction <= 32'h016d202d;
8'd17: Instruction <= 32'h02449020;
8'd18: Instruction <= 32'h014e982d;
8'd19: Instruction <= 32'h016f202d;
8'd20: Instruction <= 32'h02649820;
8'd21: Instruction <= 32'h0240982e;
8'd22: Instruction <= 32'hac100020;
8'd23: Instruction <= 32'hac110024;
8'd24: Instruction <= 32'hac120028;
8'd25: Instruction <= 32'hac13002c;
8'd26: Instruction <= 32'h0810001a;
// -------- Paste Binary Instruction Above // -------- Paste Binary Instruction Above
default: Instruction <= 32'h00000000; default: Instruction <= 32'h00000000;
endcase endcase

11
sources_1/imports/single-cycle/RegisterFile.v
View File

@ -3,13 +3,10 @@ module RegisterFile(
input reset , input reset ,
input clk , input clk ,
input RegWrite , input RegWrite ,
input Regwrite2 ,
input [5 -1:0] Read_register1 , input [5 -1:0] Read_register1 ,
input [5 -1:0] Read_register2 , input [5 -1:0] Read_register2 ,
input [5 -1:0] Write_register , input [5 -1:0] Write_register ,
input [5 -1:0] Write_register2,
input [32 -1:0] Write_data , input [32 -1:0] Write_data ,
input [32 -1:0] Write_data2 ,
output [32 -1:0] Read_data1 , output [32 -1:0] Read_data1 ,
output [32 -1:0] Read_data2 output [32 -1:0] Read_data2
); );
@ -28,12 +25,8 @@ module RegisterFile(
if (reset) if (reset)
for (i = 1; i < 32; i = i + 1) for (i = 1; i < 32; i = i + 1)
RF_data[i] <= 32'h00000000; RF_data[i] <= 32'h00000000;
else else if (RegWrite && (Write_register != 5'b00000))
begin
if (RegWrite && (Write_register != 5'b00000))
RF_data[Write_register] <= Write_data; RF_data[Write_register] <= Write_data;
if (Regwrite2 && (Write_register2 != 5'b00000))
RF_data[Write_register2] <= Write_data2;
end
endmodule endmodule