module ALU(
	input [32 -1:0] in1      , 
	input [32 -1:0] in2      ,
	input [5 -1:0] ALUCtl    ,
	input Sign               ,
	output reg [32 -1:0] out, out2,
	output zero
);
    reg signed [7:0] in11,in12,in13,in14,in21,in22,in23,in24;
    reg [31:0] MACout;
	reg signed [31:0] in1s, in2s;
	// zero means whether the output is zero or not
	assign zero = (out == 0);
	
	wire ss;
	assign ss = {in1[31], in2[31]};
	
	wire lt_31;
	assign lt_31 = (in1[30:0] < in2[30:0]);
	
	// lt_signed means whether (in1 < in2)
	wire lt_signed;
	assign lt_signed = (in1[31] ^ in2[31])? 
		((ss == 2'b01)? 0: 1): lt_31;

    always @(*)
        begin
            in11=in1[31:24];
            in12=in1[23:16];
            in13=in1[15:8];
            in14=in1[7:0];
            in21=in2[31:24];
            in22=in2[23:16];
            in23=in2[15:8];
            in24=in2[7:0];
            MACout=in11*in21+in12*in22+in13*in23+in14*in24;
        end	

	// different ALU operations
	always @(*)
		case (ALUCtl)
			5'b00000: out <= in1 & in2;
			5'b00001: out <= in1 | in2;
			5'b00010: out <= in1 + in2;
			5'b00110: out <= in1 - in2;
			5'b00111: out <= {31'h00000000, Sign? lt_signed: (in1 < in2)};
			5'b01100: out <= ~(in1 | in2);
			5'b01101: out <= in1 ^ in2;
			5'b10000: out <= (in2 << in1[4:0]);
			5'b11000: out <= (in2 >> in1[4:0]);
			5'b11001: out <= ({{32{in2[31]}}, in2} >> in1[4:0]);
			5'b11010: out <= in1 * in2; // mul
			5'b11011: out <= MACout;
			5'b11100: out <= in1s>0?in1s:0;
			default: out <= 32'h00000000;
		endcase
	always @(*)
		begin
			in1s <= in1;
			in2s <= in2;
		end
	always @(*)
		case(ALUCtl)
			5'b11100: out2 <= in2s>0?in2s:0;
			default: out2 <= 32'h00000000;
		endcase

	
	
endmodule