60 lines
1.5 KiB
Verilog
60 lines
1.5 KiB
Verilog
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module ALUControl(
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input [4 -1:0] ALUOp ,
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input [6 -1:0] Funct ,
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output reg [5 -1:0] ALUCtl ,
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output Sign
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);
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// funct number for different operation
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parameter aluAND = 5'b00000;
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parameter aluOR = 5'b00001;
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parameter aluADD = 5'b00010;
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parameter aluSUB = 5'b00110;
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parameter aluSLT = 5'b00111;
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parameter aluNOR = 5'b01100;
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parameter aluXOR = 5'b01101;
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parameter aluSLL = 5'b10000;
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parameter aluSRL = 5'b11000;
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parameter aluSRA = 5'b11001;
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parameter aluMUL = 5'b11010; //mul
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// Sign means whether the ALU treats the input as a signed number or an unsigned number
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assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3];
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// set aluFunct
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reg [4:0] aluFunct;
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always @(*)
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case (Funct)
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6'b00_0000: aluFunct <= aluSLL;
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6'b00_0010: aluFunct <= aluSRL;
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6'b00_0011: aluFunct <= aluSRA;
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6'b10_0000: aluFunct <= aluADD;
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6'b10_0001: aluFunct <= aluADD;
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6'b10_0010: aluFunct <= aluSUB;
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6'b10_0011: aluFunct <= aluSUB;
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6'b10_0100: aluFunct <= aluAND;
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6'b10_0101: aluFunct <= aluOR;
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6'b10_0110: aluFunct <= aluXOR;
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6'b10_0111: aluFunct <= aluNOR;
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6'b10_1010: aluFunct <= aluSLT;
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6'b10_1011: aluFunct <= aluSLT;
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default: aluFunct <= aluADD;
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endcase
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// set ALUCtrl
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always @(*)
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case (ALUOp[2:0])
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3'b000: ALUCtl <= aluADD;
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3'b001: ALUCtl <= aluSUB;
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3'b100: ALUCtl <= aluAND;
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3'b101: ALUCtl <= aluSLT;
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3'b010: ALUCtl <= aluFunct;
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3'b110: ALUCtl <= aluMUL; //mul
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default: ALUCtl <= aluADD;
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endcase
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endmodule
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