27 lines
881 B
Verilog
27 lines
881 B
Verilog
module InstructionMemory(
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input [32 -1:0] Address,
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output reg [32 -1:0] Instruction
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);
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always @(*)
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case (Address[9:2])
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// -------- Paste Binary Instruction Below (Inst-q1-1/Inst-q1-2.txt)
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8'd0: Instruction <= 32'h20040000;
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8'd1: Instruction <= 32'h20050020;
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8'd2: Instruction <= 32'h20100000;
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8'd3: Instruction <= 32'h8c880000;
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8'd4: Instruction <= 32'h8c890004;
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8'd5: Instruction <= 32'h71095002;
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8'd6: Instruction <= 32'h020a8020;
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8'd7: Instruction <= 32'h20840008;
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8'd8: Instruction <= 32'h10850001;
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8'd9: Instruction <= 32'h08100003;
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8'd10: Instruction <= 32'hacb00000;
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8'd11: Instruction <= 32'h0810000b;
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// -------- Paste Binary Instruction Above
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default: Instruction <= 32'h00000000;
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endcase
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endmodule
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