155 lines
4.1 KiB
Verilog
155 lines
4.1 KiB
Verilog
module CPU(
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input reset ,
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input clk ,
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output MemRead ,
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output MemWrite ,
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output [32 -1:0] MemBus_Address ,
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output [32 -1:0] MemBus_Write_Data ,
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input [32 -1:0] Device_Read_Data
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);
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// PC register
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reg [31 :0] PC;
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wire [31 :0] PC_next;
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wire [31 :0] PC_plus_4;
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always @(posedge reset or posedge clk)
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if (reset)
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PC <= 32'h00000000;
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else
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PC <= PC_next;
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assign PC_plus_4 = PC + 32'd4;
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// Instruction Memory
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wire [31 :0] Instruction;
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InstructionMemory instruction_memory1(
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.Address (PC ),
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.Instruction (Instruction )
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);
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// Control
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wire [2 -1:0] RegDst ;
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wire [2 -1:0] PCSrc ;
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wire Branch ;
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wire MemRead ;
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wire MemWrite ;
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wire [2 -1:0] MemtoReg ;
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wire ALUSrc1 ;
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wire ALUSrc2 ;
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wire [4 -1:0] ALUOp ;
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wire ExtOp ;
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wire LuOp ;
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wire RegWrite ;
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Control control1(
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.OpCode (Instruction[31:26] ),
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.Funct (Instruction[5 : 0] ),
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.PCSrc (PCSrc ),
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.Branch (Branch ),
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.RegWrite (RegWrite ),
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.RegDst (RegDst ),
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.MemRead (MemRead ),
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.MemWrite (MemWrite ),
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.MemtoReg (MemtoReg ),
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.ALUSrc1 (ALUSrc1 ),
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.ALUSrc2 (ALUSrc2 ),
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.ExtOp (ExtOp ),
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.LuOp (LuOp ),
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.ALUOp (ALUOp )
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);
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// Register File
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wire [32 -1:0] Databus1;
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wire [32 -1:0] Databus2;
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wire [32 -1:0] Databus3;
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wire [5 -1:0] Write_register;
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assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: (RegDst == 2'b01)? Instruction[15:11]: 5'b11111;
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RegisterFile register_file1(
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.reset (reset ),
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.clk (clk ),
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.RegWrite (RegWrite ),
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.Read_register1 (Instruction[25:21] ),
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.Read_register2 (Instruction[20:16] ),
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.Write_register (Write_register ),
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.Write_data (Databus3 ),
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.Read_data1 (Databus1 ),
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.Read_data2 (Databus2 )
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);
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// Extend
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wire [32 -1:0] Ext_out;
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assign Ext_out = { ExtOp? {16{Instruction[15]}}: 16'h0000, Instruction[15:0]};
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wire [32 -1:0] LU_out;
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assign LU_out = LuOp? {Instruction[15:0], 16'h0000}: Ext_out;
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// ALU Control
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wire [5 -1:0] ALUCtl;
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wire Sign ;
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ALUControl alu_control1(
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.ALUOp (ALUOp ),
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.Funct (Instruction[5:0] ),
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.ALUCtl (ALUCtl ),
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.Sign (Sign )
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);
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// ALU
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wire [32 -1:0] ALU_in1;
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wire [32 -1:0] ALU_in2;
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wire [32 -1:0] ALU_out;
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wire Zero ;
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assign ALU_in1 = ALUSrc1? {27'h00000, Instruction[10:6]}: Databus1;
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assign ALU_in2 = ALUSrc2? LU_out: Databus2;
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ALU alu1(
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.in1 (ALU_in1 ),
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.in2 (ALU_in2 ),
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.ALUCtl (ALUCtl ),
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.Sign (Sign ),
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.out (ALU_out ),
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.zero (Zero )
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);
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// Data Memory
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wire [32 -1:0] Memory_Read_Data ;
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wire Memory_Read ;
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wire Memory_Write ;
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wire [32 -1:0] MemBus_Read_Data ;
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DataMemory data_memory1(
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.reset (reset ),
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.clk (clk ),
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.Address (MemBus_Address ),
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.Write_data (MemBus_Write_Data ),
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.Read_data (Memory_Read_Data ),
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.MemRead (Memory_Read ),
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.MemWrite (Memory_Write )
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);
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assign Memory_Read = MemRead ;
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assign Memory_Write = MemWrite;
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assign MemBus_Address = ALU_out ;
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assign MemBus_Write_Data = Databus2;
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assign MemBus_Read_Data = Memory_Read_Data;
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// write back
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assign Databus3 = (MemtoReg == 2'b00)? ALU_out: (MemtoReg == 2'b01)? MemBus_Read_Data: PC_plus_4;
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// PC jump and branch
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wire [32 -1:0] Jump_target;
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assign Jump_target = {PC_plus_4[31:28], Instruction[25:0], 2'b00};
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wire [32 -1:0] Branch_target;
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assign Branch_target = (Branch & Zero)? PC_plus_4 + {LU_out[29:0], 2'b00}: PC_plus_4;
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assign PC_next = (PCSrc == 2'b00)? Branch_target: (PCSrc == 2'b01)? Jump_target: Databus1;
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endmodule
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