31 lines
675 B
Verilog
31 lines
675 B
Verilog
module test_cpu();
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reg reset ;
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reg clk ;
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wire MemRead ;
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wire MemWrite ;
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wire [31:0] MemBus_Address ;
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wire [31:0] MemBus_Write_Data ;
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wire [31:0] Device_Read_Data ;
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CPU cpu1(
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.reset (reset ),
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.clk (clk ),
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.MemBus_Address (MemBus_Address ),
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.Device_Read_Data (Device_Read_Data ),
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.MemBus_Write_Data (MemBus_Write_Data ),
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.MemRead (MemRead ),
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.MemWrite (MemWrite )
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);
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initial begin
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reset = 1;
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clk = 1;
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#100 reset = 0;
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end
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always #50 clk = ~clk;
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endmodule
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