56 lines
1.5 KiB
Verilog
56 lines
1.5 KiB
Verilog
module DataMemory(
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input reset ,
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input clk ,
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input MemRead ,
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input MemWrite ,
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input [32 -1:0] Address ,
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input [32 -1:0] Write_data ,
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output [32 -1:0] Read_data
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);
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// RAM size is 256 words, each word is 32 bits, valid address is 8 bits
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parameter RAM_SIZE = 256;
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parameter RAM_SIZE_BIT = 8;
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// RAM_data is an array of 256 32-bit registers
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reg [31:0] RAM_data [RAM_SIZE - 1: 0];
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// read data from RAM_data as Read_data
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assign Read_data = MemRead? RAM_data[Address[RAM_SIZE_BIT + 1:2]]: 32'h00000000;
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// write Write_data to RAM_data at clock posedge
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integer i;
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always @(posedge reset or posedge clk)begin
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if (reset) begin
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// -------- Paste Data Memory Configuration Below (Data-q1.txt)
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// Data Input: X = [X0, X1, X2, X3]
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// Data Input: Y = [Y0, Y1, Y2, Y3]
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// Data Output: Z = mac(X, Y) = X0*Y0 + X1*Y1 + X2*Y2 + X3*Y3
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// paste in DataMemory.v
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RAM_data[0] <= 32'hffffffd3; // X0 = -45
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RAM_data[1] <= 32'h00000003; // Y0 = 3
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RAM_data[2] <= 32'h00000028; // X1 = 40
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RAM_data[3] <= 32'h00000024; // Y1 = 36
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RAM_data[4] <= 32'hfffffffe; // X2 = -2
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RAM_data[5] <= 32'h00000006; // Y2 = 6
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RAM_data[6] <= 32'hfffffff9; // X3 = -7
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RAM_data[7] <= 32'h0000003a; // Y3 = 58
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for (i = 8; i < RAM_SIZE; i = i + 1)
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RAM_data[i] <= 32'h00000000;
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// -------- Paste Data Memory Configuration Above
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end
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else if (MemWrite) begin
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RAM_data[Address[RAM_SIZE_BIT + 1:2]] <= Write_data;
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end
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end
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endmodule
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