77 lines
1.9 KiB
Verilog
77 lines
1.9 KiB
Verilog
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module Control(
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input [6 -1:0] OpCode ,
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input [6 -1:0] Funct ,
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output [2 -1:0] PCSrc ,
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output Branch ,
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output RegWrite ,
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output RegWrite2 ,
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output ReadFrom ,
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output [2 -1:0] RegDst ,
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output MemRead ,
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output MemWrite ,
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output [2 -1:0] MemtoReg ,
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output ALUSrc1 ,
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output ALUSrc2 ,
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output ExtOp ,
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output LuOp ,
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output [4 -1:0] ALUOp
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);
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// Your code below (for question 1)
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assign PCSrc =
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(OpCode == 6'h00 && Funct == 6'h08)? 2'b10:
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(OpCode == 6'h02 || OpCode == 6'h03)? 2'b01:
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2'b00;
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assign Branch = (OpCode == 6'h04)? 1'b1: 1'b0;
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assign RegWrite =
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(OpCode == 6'h2b || OpCode == 6'h04 || OpCode == 6'h02)? 1'b0:
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(OpCode == 6'h00 && Funct == 6'h08)? 1'b0:
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1'b1;
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assign RegWrite2 =
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(OpCode == 6'h00 && Funct == 6'h2e)? 1'b1:
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1'b0;
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assign ReadFrom =
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(OpCode == 6'h00 || OpCode == 6'h2e)? 1'b1:
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1'b0;
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assign RegDst =
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(OpCode[5:3] == 3'b001)? 2'b00:
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(OpCode == 6'h23)? 2'b00:
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(OpCode == 6'h03)? 2'b10:
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(OpCode == 6'h2e)? 2'b11:
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2'b01;
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assign MemRead = (OpCode == 6'h23)? 1'b1: 1'b0;
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assign MemWrite = (OpCode == 6'h2b)? 1'b1: 1'b0;
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assign MemtoReg =
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(OpCode == 6'h23)? 2'b01:
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(OpCode == 6'h03)? 2'b10:
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2'b00;
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assign ALUSrc1 = (OpCode == 6'h00 && Funct[5:2] == 4'b0000)? 1'b1: 1'b0;
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assign ALUSrc2 =
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(OpCode[5:3] == 3'b001)? 1'b1:
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(OpCode == 6'h23 || OpCode == 6'h2b)? 1'b1:
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1'b0;
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assign ExtOp =
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(OpCode == 6'h0c)? 1'b0:
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1'b1;
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assign LuOp =
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(OpCode == 6'h0f)? 1'b1:
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1'b0;
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// Your code above (for question 1)
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// set ALUOp
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assign ALUOp[2:0] =
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(OpCode == 6'h00)? 3'b010:
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(OpCode == 6'h04)? 3'b001:
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(OpCode == 6'h0c)? 3'b100:
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(OpCode == 6'h0a || OpCode == 6'h0b)? 3'b101:
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(OpCode == 6'h1c && Funct == 6'h02)? 3'b110:
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3'b000; //mul
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assign ALUOp[3] = OpCode[0];
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endmodule |