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ClF3 2024-06-30 23:01:11 +08:00
parent 1be7b4b14e
commit 6db5db52e4
6 changed files with 58 additions and 17 deletions
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15
sources_1/imports/single-cycle/ALU.v
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@ -4,11 +4,12 @@ module ALU(
input [32 -1:0] in2 , input [32 -1:0] in2 ,
input [5 -1:0] ALUCtl , input [5 -1:0] ALUCtl ,
input Sign , input Sign ,
output reg [32 -1:0] out , output reg [32 -1:0] out, out2,
output zero output zero
); );
reg signed [7:0] in11,in12,in13,in14,in21,in22,in23,in24; reg signed [7:0] in11,in12,in13,in14,in21,in22,in23,in24;
reg [31:0] MACout; reg [31:0] MACout;
reg signed [31:0] in1s, in2s;
// zero means whether the output is zero or not // zero means whether the output is zero or not
assign zero = (out == 0); assign zero = (out == 0);
@ -51,10 +52,20 @@ module ALU(
5'b11001: out <= ({{32{in2[31]}}, in2} >> in1[4:0]); 5'b11001: out <= ({{32{in2[31]}}, in2} >> in1[4:0]);
5'b11010: out <= in1 * in2; // mul 5'b11010: out <= in1 * in2; // mul
5'b11011: out <= MACout; 5'b11011: out <= MACout;
5'b11100: out <= in1s>0?in1s:0;
default: out <= 32'h00000000; default: out <= 32'h00000000;
endcase endcase
always @(*)
begin
in1s <= in1;
in2s <= in2;
end
always @(*)
case(ALUCtl)
5'b11100: out2 <= in2s>0?in2s:0;
default: out2 <= 32'h00000000;
endcase
endmodule endmodule

2
sources_1/imports/single-cycle/ALUControl.v
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@ -20,6 +20,7 @@ module ALUControl(
parameter aluSRA = 5'b11001; parameter aluSRA = 5'b11001;
parameter aluMUL = 5'b11010; //mul parameter aluMUL = 5'b11010; //mul
parameter aluMAC = 5'b11011; parameter aluMAC = 5'b11011;
parameter aluRELU= 5'b11100;
// Sign means whether the ALU treats the input as a signed number or an unsigned number // Sign means whether the ALU treats the input as a signed number or an unsigned number
assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3]; assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3];
@ -42,6 +43,7 @@ module ALUControl(
6'b10_1010: aluFunct <= aluSLT; 6'b10_1010: aluFunct <= aluSLT;
6'b10_1011: aluFunct <= aluSLT; 6'b10_1011: aluFunct <= aluSLT;
6'b10_1101: aluFunct <= aluMAC; 6'b10_1101: aluFunct <= aluMAC;
6'b10_1110: aluFunct <= aluRELU;
default: aluFunct <= aluADD; default: aluFunct <= aluADD;
endcase endcase

15
sources_1/imports/single-cycle/CPU.v
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@ -29,6 +29,7 @@ module CPU(
); );
// Control // Control
wire ReadFrom ;
wire [2 -1:0] RegDst ; wire [2 -1:0] RegDst ;
wire [2 -1:0] PCSrc ; wire [2 -1:0] PCSrc ;
wire Branch ; wire Branch ;
@ -41,6 +42,7 @@ module CPU(
wire ExtOp ; wire ExtOp ;
wire LuOp ; wire LuOp ;
wire RegWrite ; wire RegWrite ;
wire RegWrite2 ;
Control control1( Control control1(
.OpCode (Instruction[31:26] ), .OpCode (Instruction[31:26] ),
@ -48,6 +50,8 @@ module CPU(
.PCSrc (PCSrc ), .PCSrc (PCSrc ),
.Branch (Branch ), .Branch (Branch ),
.RegWrite (RegWrite ), .RegWrite (RegWrite ),
.RegWrite2 (RegWrite2 ),
.ReadFrom (ReadFrom ),
.RegDst (RegDst ), .RegDst (RegDst ),
.MemRead (MemRead ), .MemRead (MemRead ),
.MemWrite (MemWrite ), .MemWrite (MemWrite ),
@ -63,18 +67,24 @@ module CPU(
wire [32 -1:0] Databus1; wire [32 -1:0] Databus1;
wire [32 -1:0] Databus2; wire [32 -1:0] Databus2;
wire [32 -1:0] Databus3; wire [32 -1:0] Databus3;
wire [32 -1:0] Databus4;
wire [5 -1:0] Write_register; wire [5 -1:0] Write_register;
wire [5 -1:0] Read_register2;
assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: (RegDst == 2'b01)? Instruction[15:11]: 5'b11111; assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: (RegDst == 2'b01)? Instruction[15:11]:(RegDst == 2'b11)?Instruction[25:21]:5'b11111;
assign Read_register2 = (ReadFrom == 1'b1)? Instruction[15:11]: Instruction[20:16];
RegisterFile register_file1( RegisterFile register_file1(
.reset (reset ), .reset (reset ),
.clk (clk ), .clk (clk ),
.RegWrite (RegWrite ), .RegWrite (RegWrite ),
.Regwrite2 (RegWrite2 ),
.Read_register1 (Instruction[25:21] ), .Read_register1 (Instruction[25:21] ),
.Read_register2 (Instruction[20:16] ), .Read_register2 (Read_register2 ),
.Write_register (Write_register ), .Write_register (Write_register ),
.Write_register2(Instruction[15:11] ),
.Write_data (Databus3 ), .Write_data (Databus3 ),
.Write_data2 (Databus4 ),
.Read_data1 (Databus1 ), .Read_data1 (Databus1 ),
.Read_data2 (Databus2 ) .Read_data2 (Databus2 )
); );
@ -112,6 +122,7 @@ module CPU(
.ALUCtl (ALUCtl ), .ALUCtl (ALUCtl ),
.Sign (Sign ), .Sign (Sign ),
.out (ALU_out ), .out (ALU_out ),
.out2 (Databus4 ),
.zero (Zero ) .zero (Zero )
); );

9
sources_1/imports/single-cycle/Control.v
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@ -5,6 +5,8 @@ module Control(
output [2 -1:0] PCSrc , output [2 -1:0] PCSrc ,
output Branch , output Branch ,
output RegWrite , output RegWrite ,
output RegWrite2 ,
output ReadFrom ,
output [2 -1:0] RegDst , output [2 -1:0] RegDst ,
output MemRead , output MemRead ,
output MemWrite , output MemWrite ,
@ -27,10 +29,17 @@ module Control(
(OpCode == 6'h2b || OpCode == 6'h04 || OpCode == 6'h02)? 1'b0: (OpCode == 6'h2b || OpCode == 6'h04 || OpCode == 6'h02)? 1'b0:
(OpCode == 6'h00 && Funct == 6'h08)? 1'b0: (OpCode == 6'h00 && Funct == 6'h08)? 1'b0:
1'b1; 1'b1;
assign RegWrite2 =
(OpCode == 6'h00 && Funct == 6'h2e)? 1'b1:
1'b0;
assign ReadFrom =
(OpCode == 6'h00 || OpCode == 6'h2e)? 1'b1:
1'b0;
assign RegDst = assign RegDst =
(OpCode[5:3] == 3'b001)? 2'b00: (OpCode[5:3] == 3'b001)? 2'b00:
(OpCode == 6'h23)? 2'b00: (OpCode == 6'h23)? 2'b00:
(OpCode == 6'h03)? 2'b10: (OpCode == 6'h03)? 2'b10:
(OpCode == 6'h2e)? 2'b11:
2'b01; 2'b01;
assign MemRead = (OpCode == 6'h23)? 1'b1: 1'b0; assign MemRead = (OpCode == 6'h23)? 1'b1: 1'b0;
assign MemWrite = (OpCode == 6'h2b)? 1'b1: 1'b0; assign MemWrite = (OpCode == 6'h2b)? 1'b1: 1'b0;

25
sources_1/imports/single-cycle/InstructionMemory.v
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@ -21,17 +21,20 @@ module InstructionMemory(
8'd11: Instruction <= 32'h010e882d; 8'd11: Instruction <= 32'h010e882d;
8'd12: Instruction <= 32'h012f202d; 8'd12: Instruction <= 32'h012f202d;
8'd13: Instruction <= 32'h02248820; 8'd13: Instruction <= 32'h02248820;
8'd14: Instruction <= 32'h014c902d; 8'd14: Instruction <= 32'h0200882e;
8'd15: Instruction <= 32'h016d202d; 8'd15: Instruction <= 32'h014c902d;
8'd16: Instruction <= 32'h02449020; 8'd16: Instruction <= 32'h016d202d;
8'd17: Instruction <= 32'h014e982d; 8'd17: Instruction <= 32'h02449020;
8'd18: Instruction <= 32'h016f202d; 8'd18: Instruction <= 32'h014e982d;
8'd19: Instruction <= 32'h02649820; 8'd19: Instruction <= 32'h016f202d;
8'd20: Instruction <= 32'hac100020; 8'd20: Instruction <= 32'h02649820;
8'd21: Instruction <= 32'hac110024; 8'd21: Instruction <= 32'h0240982e;
8'd22: Instruction <= 32'hac120028; 8'd22: Instruction <= 32'hac100020;
8'd23: Instruction <= 32'hac13002c; 8'd23: Instruction <= 32'hac110024;
8'd24: Instruction <= 32'h08100018; 8'd24: Instruction <= 32'hac120028;
8'd25: Instruction <= 32'hac13002c;
8'd26: Instruction <= 32'h0810001a;
// -------- Paste Binary Instruction Above // -------- Paste Binary Instruction Above
default: Instruction <= 32'h00000000; default: Instruction <= 32'h00000000;
endcase endcase

5
sources_1/imports/single-cycle/RegisterFile.v
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@ -3,10 +3,13 @@ module RegisterFile(
input reset , input reset ,
input clk , input clk ,
input RegWrite , input RegWrite ,
input Regwrite2 ,
input [5 -1:0] Read_register1 , input [5 -1:0] Read_register1 ,
input [5 -1:0] Read_register2 , input [5 -1:0] Read_register2 ,
input [5 -1:0] Write_register , input [5 -1:0] Write_register ,
input [5 -1:0] Write_register2,
input [32 -1:0] Write_data , input [32 -1:0] Write_data ,
input [32 -1:0] Write_data2 ,
output [32 -1:0] Read_data1 , output [32 -1:0] Read_data1 ,
output [32 -1:0] Read_data2 output [32 -1:0] Read_data2
); );
@ -27,6 +30,8 @@ module RegisterFile(
RF_data[i] <= 32'h00000000; RF_data[i] <= 32'h00000000;
else if (RegWrite && (Write_register != 5'b00000)) else if (RegWrite && (Write_register != 5'b00000))
RF_data[Write_register] <= Write_data; RF_data[Write_register] <= Write_data;
else if (Regwrite2 && (Write_register2 != 5'b00000))
RF_data[Write_register2] <= Write_data2;
endmodule endmodule