71 lines
1.7 KiB
Verilog
71 lines
1.7 KiB
Verilog
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module ALU(
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input [32 -1:0] in1 ,
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input [32 -1:0] in2 ,
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input [5 -1:0] ALUCtl ,
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input Sign ,
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output reg [32 -1:0] out, out2,
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output zero
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);
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reg signed [7:0] in11,in12,in13,in14,in21,in22,in23,in24;
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reg [31:0] MACout;
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reg signed [31:0] in1s, in2s;
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// zero means whether the output is zero or not
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assign zero = (out == 0);
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wire ss;
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assign ss = {in1[31], in2[31]};
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wire lt_31;
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assign lt_31 = (in1[30:0] < in2[30:0]);
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// lt_signed means whether (in1 < in2)
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wire lt_signed;
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assign lt_signed = (in1[31] ^ in2[31])?
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((ss == 2'b01)? 0: 1): lt_31;
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always @(*)
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begin
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in11=in1[31:24];
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in12=in1[23:16];
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in13=in1[15:8];
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in14=in1[7:0];
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in21=in2[31:24];
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in22=in2[23:16];
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in23=in2[15:8];
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in24=in2[7:0];
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MACout=in11*in21+in12*in22+in13*in23+in14*in24;
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end
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// different ALU operations
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always @(*)
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case (ALUCtl)
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5'b00000: out <= in1 & in2;
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5'b00001: out <= in1 | in2;
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5'b00010: out <= in1 + in2;
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5'b00110: out <= in1 - in2;
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5'b00111: out <= {31'h00000000, Sign? lt_signed: (in1 < in2)};
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5'b01100: out <= ~(in1 | in2);
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5'b01101: out <= in1 ^ in2;
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5'b10000: out <= (in2 << in1[4:0]);
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5'b11000: out <= (in2 >> in1[4:0]);
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5'b11001: out <= ({{32{in2[31]}}, in2} >> in1[4:0]);
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5'b11010: out <= in1 * in2; // mul
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5'b11011: out <= MACout;
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5'b11100: out <= in1s>0?in1s:0;
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default: out <= 32'h00000000;
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endcase
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always @(*)
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begin
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in1s <= in1;
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in2s <= in2;
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end
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always @(*)
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case(ALUCtl)
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5'b11100: out2 <= in2s>0?in2s:0;
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default: out2 <= 32'h00000000;
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endcase
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endmodule |