recover to q1
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@ -7,8 +7,6 @@ module ALU(
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output reg [32 -1:0] out ,
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output zero
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);
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reg signed [7:0] in11,in12,in13,in14,in21,in22,in23,in24;
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reg [31:0] MACout;
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// zero means whether the output is zero or not
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assign zero = (out == 0);
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@ -23,18 +21,7 @@ module ALU(
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assign lt_signed = (in1[31] ^ in2[31])?
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((ss == 2'b01)? 0: 1): lt_31;
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always @(*)
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begin
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in11=in1[31:24];
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in12=in1[23:16];
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in13=in1[15:8];
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in14=in1[7:0];
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in21=in2[31:24];
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in22=in2[23:16];
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in23=in2[15:8];
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in24=in2[7:0];
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MACout=in11*in21+in12*in22+in13*in23+in14*in24;
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end
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// different ALU operations
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always @(*)
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@ -50,7 +37,6 @@ module ALU(
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5'b11000: out <= (in2 >> in1[4:0]);
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5'b11001: out <= ({{32{in2[31]}}, in2} >> in1[4:0]);
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5'b11010: out <= in1 * in2; // mul
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5'b11011: out <= MACout;
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default: out <= 32'h00000000;
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endcase
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@ -19,7 +19,6 @@ module ALUControl(
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parameter aluSRL = 5'b11000;
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parameter aluSRA = 5'b11001;
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parameter aluMUL = 5'b11010; //mul
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parameter aluMAC = 5'b11011;
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// Sign means whether the ALU treats the input as a signed number or an unsigned number
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assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3];
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@ -41,7 +40,6 @@ module ALUControl(
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6'b10_0111: aluFunct <= aluNOR;
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6'b10_1010: aluFunct <= aluSLT;
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6'b10_1011: aluFunct <= aluSLT;
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6'b10_1101: aluFunct <= aluMAC;
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default: aluFunct <= aluADD;
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endcase
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@ -23,27 +23,25 @@ module DataMemory(
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always @(posedge reset or posedge clk)begin
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if (reset) begin
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// -------- Paste Data Memory Configuration Below (Data-q1.txt)
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// Data Input: X = [[X11, X12, X13, X14, X15, X16, X17, X18], [X21, X22, X23, X24, X25, X26, X27, X28]]
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// Data Input: Y = [[Y11, Y12], [Y21, Y22], [Y31, Y32], [Y41, Y42], [Y51, Y52], [Y61, Y62], [Y71, Y72], [Y81, Y82]]
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// Data Input: X = [X0, X1, X2, X3]
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// Data Input: Y = [Y0, Y1, Y2, Y3]
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// Data Output: Z = matmul(X,Y) = [[Z11, Z12], [Z21, Z22]]
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// Calculation in cpu: Z11 = X11*Y11 + X12*Y21 + X13*Y31 + X14*Y41 + X15*Y51 + X16*Y61 + X17*Y71 + X18*Y81
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// Calculation in cpu: Z12 = X11*Y12 + X12*Y22 + X13*Y32 + X14*Y42 + X15*Y52 + X16*Y62 + X17*Y72 + X18*Y82
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// Calculation in cpu: Z21 = X21*Y11 + X22*Y21 + X23*Y31 + X24*Y41 + X25*Y51 + X26*Y61 + X27*Y71 + X28*Y81
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// Calculation in cpu: Z22 = X21*Y12 + X22*Y22 + X23*Y32 + X24*Y42 + X25*Y52 + X26*Y62 + X27*Y72 + X28*Y82
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// Data Output: Z = mac(X, Y) = X0*Y0 + X1*Y1 + X2*Y2 + X3*Y3
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// paste in DataMemory.v
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RAM_data[0] <= 32'hd328fef9; // X11, X12, X13, X14, to be stored in $t0
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RAM_data[1] <= 32'h0324063a; // X15, X16, X17, X18, to be stored in $t1
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RAM_data[2] <= 32'h12da0c13; // X21, X22, X23, X24, to be stored in $t2
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RAM_data[3] <= 32'hde1015d6; // X25, X26, X27, X28, to be stored in $t3
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RAM_data[0] <= 32'hffffffd3; // X0 = -45
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RAM_data[1] <= 32'h00000003; // Y0 = 3
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RAM_data[4] <= 32'hdaf20624; // Y11, Y21, Y31, Y41, to be stored in $t4
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RAM_data[5] <= 32'hc31f27c9; // Y51, Y61, Y71, Y81, to be stored in $t5
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RAM_data[6] <= 32'h3ce4c0c6; // Y12, Y22, Y32, Y42, to be stored in $t6
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RAM_data[7] <= 32'h12ea09c2; // Y52, Y62, Y72, Y82, to be stored in $t7
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RAM_data[2] <= 32'h00000028; // X1 = 40
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RAM_data[3] <= 32'h00000024; // Y1 = 36
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RAM_data[4] <= 32'hfffffffe; // X2 = -2
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RAM_data[5] <= 32'h00000006; // Y2 = 6
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RAM_data[6] <= 32'hfffffff9; // X3 = -7
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RAM_data[7] <= 32'h0000003a; // Y3 = 58
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for (i = 8; i < RAM_SIZE; i = i + 1)
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RAM_data[i] <= 32'h00000000;
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@ -7,31 +7,18 @@ module InstructionMemory(
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case (Address[9:2])
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// -------- Paste Binary Instruction Below (Inst-q1-1/Inst-q1-2.txt)
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8'd0: Instruction <= 32'h8c080000;
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8'd1: Instruction <= 32'h8c090004;
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8'd2: Instruction <= 32'h8c0a0008;
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8'd3: Instruction <= 32'h8c0b000c;
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8'd4: Instruction <= 32'h8c0c0010;
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8'd5: Instruction <= 32'h8c0d0014;
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8'd6: Instruction <= 32'h8c0e0018;
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8'd7: Instruction <= 32'h8c0f001c;
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8'd8: Instruction <= 32'h010c802d;
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8'd9: Instruction <= 32'h012d202d;
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8'd10: Instruction <= 32'h02048020;
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8'd11: Instruction <= 32'h010e882d;
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8'd12: Instruction <= 32'h012f202d;
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8'd13: Instruction <= 32'h02248820;
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8'd14: Instruction <= 32'h014c902d;
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8'd15: Instruction <= 32'h016d202d;
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8'd16: Instruction <= 32'h02449020;
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8'd17: Instruction <= 32'h014e982d;
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8'd18: Instruction <= 32'h016f202d;
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8'd19: Instruction <= 32'h02649820;
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8'd20: Instruction <= 32'hac100020;
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8'd21: Instruction <= 32'hac110024;
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8'd22: Instruction <= 32'hac120028;
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8'd23: Instruction <= 32'hac13002c;
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8'd24: Instruction <= 32'h08100018;
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8'd0: Instruction <= 32'h20040000;
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8'd1: Instruction <= 32'h20050020;
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8'd2: Instruction <= 32'h20100000;
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8'd3: Instruction <= 32'h8c880000;
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8'd4: Instruction <= 32'h8c890004;
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8'd5: Instruction <= 32'h71095002;
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8'd6: Instruction <= 32'h020a8020;
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8'd7: Instruction <= 32'h20840008;
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8'd8: Instruction <= 32'h10850001;
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8'd9: Instruction <= 32'h08100003;
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8'd10: Instruction <= 32'hacb00000;
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8'd11: Instruction <= 32'h0810000b;
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// -------- Paste Binary Instruction Above
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default: Instruction <= 32'h00000000;
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endcase
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